The present invention relates to an information processing device and, particularly, to an information processing device that includes a plurality of processor elements.
A VLIW (Very Long Instruction Word) processor that allows a plurality of operation instructions to be included in an operation instruction issued at a time has been proposed recently. In instruction codes executed by the VLIW processor, operations that can be executed in parallel in programs are extracted by a compiler. The VLIW processor fetches a plurality of instruction codes that can be executed in parallel and stores them into an instruction register, and decodes the plurality of instruction codes all at once. Then, the VLIW processor causes a plurality of arithmetic units to operate in parallel based on the plurality of operation instructions generated by the decoding.
For example, in applications such as image processing, because calculation used for processing is finite and the same calculation is repeated in many cases, operations that can be executed in parallel can be easily extracted. Therefore, the VLIW processor is effectively used particularly in applications such as image processing. An example of the VLIW processor is disclosed in S. Kyo, et al., “A Low-Cost Mixed-Mode Parallel Processor Architecture for Embedded Systems”, Proc. of ACM Int. Conf. on Supercomputing, pp. 253-262, June, 2007 (which is hereinafter referred to as Kyo et al.). The processor described in Kyo et al. includes a plurality of processor elements, each of them configured as the VLIW processor. With inclusion of a plurality of VLIW processors, Kyo et al. enables further improvement of throughput.